Market narratives frequently depict silicon photonics as a messianic solution for reducing power consumption in AI systems. However, this interpretation risks causing key misunderstandings. Optics do not stop GPUs from generating heat; what they truly improve are transmission distances, bandwidth density, and energy consumption per bit during high-speed data migration. As high-end AI accelerator modules cross the kilowatt power threshold and AI clusters scale beyond tens of thousands of accelerators, the factors limiting compute expansion are no longer confined to logic nodes. Instead, they have expanded to memory, network topologies, SerDes, optical interconnects, advanced packaging, thermal management, and system yield. Whether silicon photonics can genuinely penetrate the core of AI infrastructure will ultimately depend not merely on photonic device performance, but on whether optical packaging, testing, automated assembly, serviceability, and volume production costs can all pass muster simultaneously.
Recent Developments: The Hidden Compute Agenda Beyond the GTC Stage
At recent AI summits, optical communications expos, and foundry technology forums, the competitive focus of major industry players has been expanding beyond simply raising the FLOPs of individual chips. The key objective has shifted to how tens of thousands of accelerators can be integrated into an effectively operating, cohesive system.
While NVIDIA, Broadcom, and TSMC approach this challenge from different angles—compute platforms, switch ASICs, and advanced packaging, respectively—their recent public roadmaps converge on a clear signal: the bottlenecks facing AI data centers no longer reside purely in single-chip logic compute. Instead, they have broadened into memory, network topologies, SerDes, optical interconnects, power delivery, and thermal management.
Currently, large-scale AI data centers still rely primarily on 800G pluggable optical modules, while 1.6T modules are entering adoption and volume production ramp-up phases. However, as switch bandwidth and single-port rates continue to rise, pluggable architectures face mounting pressures regarding electrical transmission distances, faceplate density, and power consumption.
Consequently, the industry is progressively moving optical engines closer to switch ASICs and further exploring Optical I/O integrated directly into custom XPU, CPU, and GPU compute packages. Co-Packaged Optics (CPO) for switches are beginning to materialize as commercial products—for instance, NVIDIA expects to supply Spectrum-X Ethernet Photonics switches starting in the second half of 2026—whereas Optical I/O in compute packages remains primarily centered on technology demonstrations, custom solutions, and next-generation platform development. This is not a science communication campaign claiming that “fiber optics are faster”; it is a forced infrastructure revolution.
Evolutionary Background and Physical Limits: Why Now?
Over the past decade, silicon photonics has already seen gradual commercialization within pluggable optical modules (such as 100G, 400G, and 800G) for medium- to long-distance transmission inside data centers. The true inflection point occurring today is that optical engines are beginning to shift from pluggable modules on chassis faceplates toward switch ASICs, package substrates, and the periphery of compute chips.
The reason lies not in a sudden, drastic leap in optical technology itself, but in the fact that as single-lane SerDes speeds and system bandwidth rise, the economical transmission distance over copper interconnects that can maintain signal integrity is shrinking rapidly.
Evolutionary Trajectory: The Shift in Interconnect Boundaries
- Traditional Data Centers (Copper Dominance Zone)└─> Signals travel over copper ──> Moderate distance, manageable bandwidth demand, controllable resistive heating (Feasible)
- Modern Multi-Ten-Thousand Accelerator AI Clusters (Electrical Interconnect Bottleneck)└─> High-end compute modules cross the kilowatt power mark ──> Ultra-high-speed signals travel over copper ──> Severe high-frequency loss, surging SerDes power, difficult cable maintenance and airflow management (Uncontrolled cost and energy consumption)
- Next-Generation Optoelectronic Co-existence (CPO / Optical I/O)└─> Short distances utilize electrical signals for compute and transport ──> Electro-optic conversion occurs at the package edge or near the ASIC ──> Longer distances connected via optical fiber (Tiered co-existence)
- AI Compute Module Power Surpassing the Kilowatt Mark: When high-end AI compute modules approach or exceed 1000W, systems can no longer tolerate interconnect power consumption scaling proportionally with bandwidth. The issue is not a lack of power budget for SerDes, but that energy consumption per bit transmitted (pJ/bit) must continuously and significantly decrease.
- Physical Attenuation of High-Frequency Electrical Signals: As SerDes rates increase, copper interconnects suffer from deteriorating conductor loss (driven by skin effect), dielectric loss, reflection, and crosstalk, drastically shortening acceptable electrical transmission distances.
- System Complexity and Airflow Management: To maintain signal integrity, systems must deploy more complex equalization, DSPs, retimers, or Active Electrical Cables (AEC). This increases power consumption and cost, while dense, high-speed copper cables add weight, bulk, and restrictive bend radii, making rack cabling, maintenance, and thermal airflow management increasingly difficult.
Copper has not suddenly “failed.” For a considerable period ahead, intra-chip and short-distance board-level transfers will remain dominated by electrical interconnects. However, in high-bandwidth, cross-rack, and high-density interconnect scenarios, bringing “light” directly adjacent to the chip has become an inescapable requirement to lower overall system operational costs.
Where Are the True Bottlenecks? Not the Laser, but Assembly and Yield
A common myth persists among the general public: “Silicon photonics develops slowly because silicon wafers cannot emit light.”
This is only half true. Heterogeneous Integration—integrating III-V compound semiconductor laser sources (such as Indium Phosphide, InP) onto silicon photonics chips—has achieved substantial engineering breakthroughs.
The real roadblocks hindering the large-scale commercialization of CPO and Optical I/O are hidden within four challenging operational aspects of manufacturing:
| Bottleneck Segment | Engineering Challenges and Realities |
|---|---|
| High-Precision Optical Assembly | Silicon photonic waveguides operate at sub-micron scales, requiring edge couplers, grating couplers, or mode-field converters to couple light efficiently from fibers into the chip. Even with these coupling structures, volume assembly must simultaneously ensure sub-micron alignment control, high repeatability, and low insertion loss. |
| Thermal Isolation and Laser Lifespan | Lasers and certain optical components are highly sensitive to heat, where high temperatures cause wavelength drift, efficiency degradation, and shortened operating lifespan. In switch CPO, optical engines sit near high-power switch ASICs; in compute Optical I/O, they lie adjacent to GPUs, CPUs, or other XPUs. Mitigating thermal coupling between light sources and high-heat logic chips—while balancing dissipation, packaging density, and serviceability—presents a major volume manufacturing challenge. |
| Testing and Yield | If an optical engine is found defective only after final packaging, it risks rendering expensive switch ASICs or compute chips unusable. Consequently, wafer-level optical testing, Known Good Die (KGD) strategies, and modular designs are essential to securing volume production economics. |
| Serviceability | Once optical engines are co-packaged with switch ASICs or compute chips, a lack of field-replaceable design means that a failure could require the entire switch board, compute module, or package assembly to be decommissioned. |
This is the true industry narrative of silicon photonics: it is no longer merely a matter of optical design, but an intense campaign involving advanced packaging, automated testing, and precision assembly.
Industry Power Realignment: Which Capabilities Are Being Redefined?
As transmission media transition from copper to light, the core value across semiconductor and telecommunications supply chains is being reallocated. Traditional optical module manufacturers will not necessarily lose relevance, but their capabilities must evolve toward optical engines, high-precision packaging, and External Laser Small Form-factor Pluggable (ELS) systems:
- Silicon Photonics PIC Manufacturing Capability: Foundries and PIC manufacturers capable of reliably fabricating low-loss waveguides, modulators, photodetectors, couplers, and associated passive components.
- Optoelectronic Interposer and Heterogeneous Integration Capability: Advanced OSATs and packaging foundries capable of integrating PICs, EICs (including drivers, TIAs, CDRs, and SerDes control circuits), and switch ASICs or XPUs into a single system via interposers, package substrates, or 3D stacking.
- Sub-Micron Optical Alignment and Automated Test Equipment: Specialized equipment vendors offering high-repeatability optical alignment and wafer-level optical testing.
- External Laser Sources (ELS) and Optical Connector Ecosystems: Suppliers delivering External Laser Modules (ELSFP) to resolve thermal issues, alongside high-density blind-mate optical connectors and Fiber Array Units (FAU).
The value chain is extending beyond basic module assembly toward silicon photonic wafers, optoelectronic co-design, advanced packaging, and automated testing.
Battles of Strategic Approaches: The Four Positions of Tech Giants
Faced with this optical transformation, industry leaders have not aligned around a single unified answer, but have instead chosen distinct strategic positions:
| Company | Strategic Positioning | Core Focus and Approach |
|---|---|---|
| Broadcom | Switch ASICs and Networking Platforms | Entering through switch ASICs and networking ecosystems, advancing CPO via its Tomahawk series (such as the shipped 102.4T Tomahawk 6 Davisson), and addressing large-scale AI fabrics through platforms like Jericho. |
| NVIDIA | AI Factory Full-Stack Systems | Integrating photonics into Ethernet, InfiniBand, and scale-up/scale-out networking architectures within its AI Factory vision. Currently centered on Spectrum-X and Quantum-X Photonics platforms (with product availability expected starting in 2026), its long-term strategy aims to extend optical interconnects from the network layer to compute interconnects, driving co-packaging of Optical I/O with compute chips. |
| Intel | Integrated Devices and Optical I/O | Leveraging long-standing developments in silicon photonics, III-V laser heterogeneous integration, and Optical I/O. Intel has demonstrated its OCI chiplet—combining integrated lasers, PICs, and EICs—co-packaged and running with Intel CPUs, targeting HPC and AI infrastructure. |
| TSMC | Wafer Fabrication and Advanced Packaging Platform | Integrating PIC, EIC, SoIC, and CoWoS technologies through its COUPE platform. TSMC plans to begin production of COUPE-on-substrate solutions in 2026, offering customers a comprehensive platform for silicon photonics and advanced packaging integration. |
Next Checkpoints: Two Critical Indicators for 2026–2027
Will this technology remain a demonstration concept at trade shows, or will it achieve broad deployment? Rather than relying on public relations statements, industry observers need to monitor two concrete validation milestones:
- Checkpoint A: Commercial Adoption of the ELSFP and External Laser EcosystemTo isolate lasers from high-temperature logic chips and improve light source serviceability, certain CPO architectures move lasers to equipment faceplates where heat dissipation and replacement are easier. The Optical Internetworking Forum (OIF) has released mechanical, optical, and management interface specifications for ELSFP (e.g., OIF-ELSFP-01.0, CMIS). If multiple switch platforms, ODMs, and Cloud Service Providers (CSPs) adopt OIF-compliant ELSFPs between 2026 and 2027, accompanied by supplier announcements of volume production, interoperability verification, and real-world deployment, it will signal that external lasers have achieved commercial validation in standardization, supply chain interoperability, and field serviceability.
- Checkpoint B: Progression of 102.4T CPO from Shipments to Multi-Customer DeploymentWith Broadcom having begun shipping its 102.4T Tomahawk 6 Davisson CPO platform, the next milestone is no longer whether CPO products can be built, but whether they can transition from early adopters to routine volume deployment across multiple CSPs, ODMs, and switch system integrators. If CPO demonstrates simultaneous viability in power efficiency, reliability, maintenance costs, and supply chain maturity, it will mark the technology crossing the bridge from engineering feasibility to commercial viability.
The Bigger Picture: Redefining the Design Philosophy of AI Infrastructure
Looking further ahead, the endpoint of the silicon photonics revolution is far broader than simply replacing copper cables with optical fibers.
If optical interconnects are fully realized at the package and system levels, the fundamental unit of system design may evolve from individual chips or standalone servers toward rack-scale architectures composed of multiple pooled compute, memory, and networking nodes.
Optical interconnects hold the potential to extend resource pooling from within individual chassis to rack levels or even across data center regions. However, different resources possess varying tolerances for distance: while storage and certain accelerator assets can be shared over longer spans, ultra-low-latency memory consistency remains strictly bound by physical limits—including the propagation speed of light in optical fiber (approximately two-thirds the speed of light in a vacuum), switching latencies, and protocol designs.
Every revolution in compute architecture redefines where value resides. What changes this time may not just be light, but the fundamental way AI infrastructure is designed, manufactured, tested, and validated.
SELECTED REFERENCES
- Broadcom Inc. (2025). Broadcom Announces Tomahawk® 6 – Davisson, the Industry’s First 102.4-Tbps Ethernet Switch with Co-Packaged Optics. Broadcom Product News Release.
- Broadcom Inc. (2026, March 12). Broadcom Showcases Industry-Leading Solutions for Scaling AI Infrastructure at OFC 2026. Broadcom Investor Relations.
- Taiwan Semiconductor Manufacturing Company (TSMC). (2026). TSMC Debuts A13 Technology at 2026 North America Technology Symposium. TSMC Newsroom / Press Release.
- NVIDIA Corporation. (2025). NVIDIA Announces Spectrum-X Photonics, Co-Packaged Optics Networking Switches to Scale AI Factories to Millions of GPUs. NVIDIA Investor Relations.
- Optical Internetworking Forum. (2024). Implementation Agreement for External Laser Small Form Factor Pluggable (ELSFP) CMIS (OIF-ELSFP-CMIS-01.0). OIF.
- Intel（2024） Intel Demonstrates First Fully Integrated Optical I/O Chiplet